Melexis engineers microelectronic solutions. These solutions facilitate the work of our customers. By easy integration. By taking innovation one step further. By providing a competitive advantage. Our technology makes cars and other products smarter, safer and greener. Our sensors capture data from the analog world and comprehend these data digitally. Our drivers make sure customers can bring their products to life. As we always have a plan, we come with the right products at the right moment so our customers stay one step ahead of the competition. That’s what we call inspired engineering.

 

 
We mainly focus on semiconductors for the automotive industry. Melexis is energizing the transition to Electrical Vehicles (EVs). We increase the efficiency of Internal Combustion Engine (ICE) cars. Besides the automotive market, we cater to other markets as well.

 
Our people are and make the difference. Melexis creates a framework for colleagues to grow, thrive and create impact for themselves, the customer and the company. Because we care, we empower and we excel. We believe in the power of diversity. Spread over 3 continents, 1900 colleagues from 50 nationalities shape the best imaginable future.

Project Description

We are developing circuits that are used in automotive safety critical systems: brakes, steering wheel, cruise control, etc… our circuits must be able to rapidly detect any anomaly in their behavior, flag it to a central ECU and if applicable enter into a safe state. In this context, the target of this  internship is to evaluate the efficiency of a minimal fault tolerant hardware on a Risc-V CPU.

You will have to learn the different hardware fault types, then become familiar with existing hardware mechanisms detecting or correcting faults (such as parity, ECC, duplication, etc...), evaluate their domain of use, performance,
silicon area and speed.

, evaluate their domain of use, performance, silicon area and speed. Once done you will have to implement in RTL the best compromises to the different sub-parts of a Risc-V CPU (ALU, registers, instruction decoder, etc…) and measure their global efficiency by simulating faults in the CPU and monitoring its response.

More specifically, you will:

● Familiarize yourself with safety concept from the ISO-26262 standard.
● Explore the state of the art of safety mechanism for CPUs.
● Implement in RTL various safety mechanisms in an existing RISC-V CPU core.
● Benchmark the area and the efficiency of each safety mechanism using synthesis and fault simulation tools.

 

Expected results

• ● An updated configurable RTL design of the RISC-V CPU core with various safety mechanisms implemented
• ● Summary of the efficiency and cost of the various safety mechanisms implemented

Your profile

• Master 2
• Basic knowledge in RTL coding (Verilog and/or VHDL)
• Basic knowledge of CPU architecture

We offer

Joining Melexis for your internship is the opportunity to build up your know-how in a high-tech, international and dynamic company, benefit from the experience and training of our experts and enjoy the welcoming and friendly atmosphere of our Paris office team which is specialized in Digital Design and counts 20 employees.